An artificial spiking synapse made of molecules and nanoparticles

Molecule-based devices are envisioned to complement silicon devices by providing new functions or already existing functions at a simpler process level and at a lower cost by virtue of their self-organization capabilities, moreover, they are not bound to von Neuman architecture and this may open the way to other architectural paradigms. Here we demonstrate a device made of conjugated molecules and metal nanoparticles (NPs) which behaves as a spiking synapse suitable for integration in neural network architectures. We demonstrate that this device exhibits the main behavior of a biological synapse. These results open the way to rate coding utilization of the NOMFET in perceptron and Hopfield networks. We can also envision the NOMFET as a building block of neuroelectronics for interfacing neurons or neuronal logic devices made from patterned neuronal cultures with solid-state devices and circuits

Gold nanoparticle-pentacene memory-transistors

We demonstrate an organic memory-transistor device based on a pentacene-gold nanoparticles active layer. Gold (Au) nanoparticles are immobilized on the gate dielectric (silicon dioxide) of a pentacene transistor by an amino-terminated self-assembled monolayer. Under the application of writing and erasing pulses on the gate, large threshold voltage shift (22 V) and on/off drain current ratio of ~3E4 are obtained. The hole field-effect mobility of the transistor is similar in the on and off states (less than a factor 2). Charge retention times up to 4500 s are observed. The memory effect is mainly attributed to the Au nanoparticles

A Compact Device Model for Nanoparticle-organic Memory Transistor’s Characterization

Neuromorphic electronic devices have recently been a candidate for new computing architecture associated with innovative nanotechnologies. A report of the characterization of Nanoparticle organic memory transistor (NOMFET) introduced a similar behavior to a biological spiking synapse in neural networks. In this paper, a refinement model based on the extracted parameters including a hybrid NOMFET/CMOS neuromorphic computing circuit and architecture of synapse to neuron interface by characterizing transistor -- memory and the temporal dynamic function is presented. A compact EKV model refinement serves as a link between nanotechnology process and circuit design for novel CMOS devices

EPICURE: A partitioning and co-design framework for reconfigurable computing

This paper presents a new design methodology able to bridge the gap between an abstract specification and a heterogeneous reconfigurable architecture. The EPICURE contribution is the result of a joint study on abstraction/refinement methods and a smart reconfigurable architecture within the formal Esterel design tools suite. The original points of this work are: (i) a generic HW/SW interface model, (ii) a specification methodology that handles the control, and includes efficient verification and HW/SW synthesis capabilities, (iii) a method for parallelism exploration based on abstract resources/performance estimation expressed in terms of area/delay tradeoffs, (iv) a HW/SW partitioning approach that refines the specification into explicit HW configurations and the associated SW control. The EPICURE framework shows how a cooperation of complementary methodologies and CAD tools associated with a relevant architecture can signficantly improve the designer productivity, especially in the context of reconfigurable architectures

Toward nano-device image processing: a neuro-inspired learning approach

National audienceAs nano-scale devices such as OG-CNTFETs are under studies and may be used in a near future, we choose to investigate in which application domain such components may be of the most interest. In this paper we present how neural networks can be used to implement functions on nano-scale components. This method has been tested in the image processing application field

Simulation of a memristor-based spiking neural network immune to device variations

International audience— We propose a design methodology to exploit adaptive nanodevices (memristors), virtually immune to their variability. Memristors are used as synapses in a spiking neural network performing unsupervised learning. The memristors learn through an adaptation of spike timing dependent plasticity. Neurons' threshold is adjusted following a homeostasis-type rule. System level simulations on a textbook case show that performance can compare with traditional supervised networks of similar complexity. They also show the system can retain functionality with extreme variations of various memristors' parameters, thanks to the robustness of the scheme, its unsupervised nature, and the power of homeostasis. Additionally the network can adjust to stimuli presented with different coding schemes

Immunity to Device Variations in a Spiking Neural Network With Memristive Nanodevices

International audience—Memristive nanodevices can feature a compact multi-level non-volatile memory function, but are prone to device variability. We propose a novel neural network-based computing paradigm, which exploits their specific physics, and which has virtual immunity to their variability. Memristive devices are used as synapses in a spiking neural network performing unsupervised learning. They learn using a simplified and customized " spike timing dependent plasticity " rule. In the network, neurons' threshold is adjusted following a homeostasis-type rule. We perform system level simulations with an experimentally verified-model of the memristive devices' behavior. They show, on the textbook case of character recognition, that performance can compare with traditional supervised networks of similar complexity. They also show that the system can retain functionality with extreme variations of various memristive devices' parameters (a relative standard dispersion of more than 50% is tolerated on all device parameters), thanks to the robustness of the scheme, its unsupervised nature, and the capability of homeostasis. Additionally the network can adjust to stimuli presented with different coding schemes, is particularly robust to read disturb effects and does not require unrealistic control on the devices' conductance. These results open the way for a novel design approach for ultra-adaptive electronic systems

Learning with memristive devices: How should we model their behavior?

International audience—This work discusses the modeling of memristive devices, for architectures where they are used as synapses. It is shown that the most common models used in this context do not always accurately reflect the actual behavior of popular devices in pulse regime. We introduce a new behavioral model, intended towards the nanoarchitecture community. It fits the conductance evolution of Univ. Michigan's synaptic memristive devices. A variation of the model fits HP labs's memristors' behavior in the same conditions. Finally, we discuss using a simple example the importance of this type of modeling for learning architectures and how it can impact the behavior of the learning

Bioinspired Programming of Memory Devices for Implementing an Inference Engine

International audience—Cognitive tasks are essential for the modern applications of electronics, and rely on the capability to perform inference. The Von Neumann bottleneck is an important issue for such tasks, and emerging memory devices offer an opportunity to overcome this issue by fusing computing and memory, in nonvolatile instant ON / OFF systems. A vision for accomplishing this is to use brain-inspired architectures, which excel at inference and do not differentiate between computing and memory. In this work, we use a neuroscience inspired model of learning, spike timing dependent plasticity, to develop a bioinspired approach for programming memory devices, which naturally gives rise to an inference engine. The method is then adapted to different memory devices, including multivalued memories (cumulative memristive device, phase change memory) and stochastic binary memories (conductive bridge memory, spin transfer torque magnetic tunnel junction). By means of system-level simulations, we investigate several applications including image recognition, and pattern detection within video and auditory data. We compare the results of the different devices. Stochastic binary devices require the use of redundancy, the extent of which depends tremendously on the considered task. A theoretical analysis allows us to understand how the various devices differ, and ties the inference engine to the machine learning algorithm of Expectation-Maximization. Monte Carlo simulations demonstrate an exceptional robustness of the inference engine with respect to device variations and other issues. A theoretical analysis explains the roots of this robustness. These results highlight a possible new bioinspired paradigm for programming emerging memory devices, allowing the natural learning of a complex inference engine. The physics of the memory devices plays an active role. The results open the way for a reinvention of the role of memory, when solving inference tasks